This invention relates to a semiconductor memory unit for use in a semiconductor memory, and more particularly to a semiconductor memory unit (hereinafter called "memory cell") of the type which stores data by temporarily holding a charge.
The so-called "dynamic RAM" (hereinafter called "DRAM") has been used widely in the past as a memory cell. FIG. 1A is a section through the structure of a DRAM, and FIG. 1B is a circuit diagram of an equivalent circuit thereof. In FIG. 1A, reference numeral 11 denotes a semiconductor substrate, 12 the gate of a switching transistor, 13 the plate of a capacitor, and 14 an impurity-doped region forming a bit line. 15 and 19 denote insulating films, and 16 denotes an impurity-doped region. Reference numerals 12', 13' and 14' in FIG. 1B correspond to reference numerals 12, 13 and 14 in FIG. 1A, respectively.
A DRAM with this structure operates in the following manner. Data is written by injecting charge into the capacitor 18 with the transistor 17 acting as a switching element. In reading mode, while the bit line 14 (14') is kept in a floating condition, the switch 17 is opened and the charge stored in the capacitor 18 is passed to the bit line 14 (14'). The change in potential of the bit line 14 (14') is then detected to determine whether or not a charge had been stored, and these two states are made to correspond to data "1" and "0".
Although DRAMs are the most commonly used memory devices at present, problems inherent to this type of device have become all the more critical as the integration density of large-scale integrated (LSI) circuits has improved, and the miniaturization of devices has increased. These problems will be described next in detail.
A first problem is that since the structure of the DRAM is such that a charge stored in a capacitor is used as the signal, the storage capacitance of the capacitors drops as the element pattern is scaled down and, together therewith, the signal strength also drops so that data read-out becomes more difficult. The ratio of storage capacitance to bit line capacitance is normally used as a quantity indicating the characteristics of a DRAM memory cell. Whereas the bit line capacitance does not usually vary much with the scale-down of the elements, the storage capacitance does drop, so that this capacitance ratio drops as the elements are scaled down, and read-out becomes difficult.
A second problem is that a DRAM is susceptible to radioactivity such as .alpha.-rays emitted from materials placed close to its chip or package, and the charges induced by radioactivity can destroy the memory cell data. This is one of the reasons why the value of the storage capacitance can not be reduced.
A third problem is that since the data stored in the DRAM memory cell is cleared when it is read out, data that is the same as the read-out data must be rewritten (refreshed). This results in another problem that the actual read-out speed of a DRAM is slow.
A memory cell called an "EPROM" (Erasable and Programmable ROM) is known as a memory cell which solves these problems. FIG. 2A shows a section through the structure of such a memory cell, and FIG. 2B, an equivalent circuit. In the drawings, reference numeral 21 denotes a semiconductor substrate, 22 a control gate, 23 a drain, 25 a source, 26 an insulating film, and 24 a floating gate. As is obvious from the drawings, an EPROM is characterized in that the floating gate 24 for storing the charge is provided between the gate 22 and the substrate 21 in a MIS (Metal Insulator Silicon) structure. This memory cell detects the logic values "1" and "0" by utilizing changes in a threshold voltage V.sub.th, viewed from the control gate, when charge is stored in the floating gate 24.
FIG. 3 shows the principle of this memory cell. Voltage V.sub.g applied to the gate is plotted along the abscissa while drain current I.sub.d is plotted along the ordinate. Curve 31 shows the characteristic of an erased condition, and curve 32 that of a written condition. In reading mode, a 5 V voltage is applied to the gate 22 and whether or not a current flows between the drain 23 and the source 25 is detected.
The first characterizing feature of an EPROM of this structure is that since the signal charge, the charge stored in the floating gate 24, is read out after being converted into a current, the quantity of this charge can be small, and hence a large storage capacitance is not necessary. The second characterizing feature is that since the charge storage portion is isolated by the insulating film, the memory cell is resistant to radioactivity such as .alpha.-rays. The third characterizing feature is that data can be read out as often as required because it is not destroyed by the read.
In comparison with a DRAM, therefore, an EPROM has various advantages and is close to being an ideal memory cell. In practice, however, EPROMs have been used exclusively as read-only memories because data is written by avalanche injection and, moreover, electrical erasure of data is not possible.